Computers and Electronic Products Industry Terminology

Agile

An iterative project management and development method emphasizing short sprints, continuous feedback, and adaptability across hardware, firmware, and software teams.

We run two-week sprints and Agile ceremonies for the firmware team.|Our Agile backlog prioritizes the PCB respin tasks.|GA slipped because Agile velocity dropped after the architecture change.

AI Accelerator

Specialized hardware (e.g., NPU, TPU) designed to speed up machine learning inference or training compared with general-purpose CPUs/GPUs.

The edge gateway includes an AI accelerator for on-device vision.|Benchmark the NPU’s TOPS before committing to the design.|Offload CNN inference to the accelerator to cut latency.

Application Programming Interface (API)

A defined set of rules for how software components interact, enabling devices, services, and apps to communicate.

Expose device telemetry via a REST API.|Our mobile app uses a gRPC API to talk to the gateway.|We version the API to avoid breaking partner integrations.

Application-Specific Integrated Circuit (ASIC)

A custom chip optimized for a specific function, offering better performance, power, or cost at volume than general-purpose parts.

We’ll tape out the ASIC at 5 nm next quarter.|The ASIC vs FPGA trade-off flips at 100k units.|A new ASIC spin will address the power regulator errata.

Automated Test Equipment (ATE)

Industrial testers and handlers used to verify semiconductor dies, packages, and assembled PCBs at scale.

Wafer sort will run on the new ATE.|Our ATE program improved test coverage to 95%.|The ATE handler throughput is the bottleneck.

Bill of Materials (BOM)

A complete, structured list of components, subassemblies, and quantities required to build a product, often with cost roll-ups.

Keep the BOM cost under $50 at 100k units.|Swap in RoHS-compliant parts across the BOM.|The BOM explosion shows the daughtercard dependencies.

Bluetooth Low Energy (BLE)

A low-power wireless standard optimized for short-range communications, common in wearables and IoT devices.

Provision the sensor nodes over BLE.|Tuning the BLE advertising interval saved battery.|We’re upgrading to BLE 5.3 for longer range.

Burn-in

A reliability screening process that stresses devices (time/temperature/load) to precipitate early-life failures before shipment.

We run 24-hour burn-in to reduce infant mortality.|Increasing burn-in temperature improved MTBF.|Burn-in fallout dropped after the solder paste change.

Channel Partner

A reseller, distributor, or systems integrator that sells or integrates your products into end-customer solutions.

We signed a channel partner in EMEA.|Channel margins are set at 20% for bundles.|Provide enablement kits to train our channel partners.

Chiplet

A modular die building block integrated with other chiplets in a single package using high-speed interconnects.

We’ll adopt a chiplet architecture on an interposer.|UCIe enables multi-vendor chiplet interoperability.|Mix a 3 nm CPU chiplet with a 6 nm I/O die.

Cloud Computing

On-demand access to compute, storage, and networking resources over the internet, typically with usage-based pricing.

Push OTA updates through our cloud.|Run analytics in the cloud, inference at the edge.|Right-size GPU instances to manage cloud spend.

Complementary Metal-Oxide-Semiconductor (CMOS)

The dominant semiconductor technology for building integrated circuits, valued for low power and high density.

Our design targets a 22 nm CMOS node.|CMOS image sensors dominate smartphones.|FinFET is a type of advanced CMOS transistor.

Contract Manufacturer (CM)

A third-party factory that builds products to your specifications, often handling procurement, assembly, and test.

Onboard a CM in Vietnam for capacity.|The CM follows our work instructions and QC plan.|We’ll audit the CM’s quality management system.

Cost of Goods Sold (COGS)

Direct costs of producing a product (materials, labor, manufacturing overhead), excluding R&D and SG&A.

Memory pricing is driving COGS volatility.|We reduced COGS by consolidating ICs.|COGS excludes the prototyping NRE.

Customer Premises Equipment (CPE)

Devices installed at a customer’s site (e.g., routers, set-top boxes, ONTs) that connect to a service provider’s network.

We’ll launch a new Wi-Fi 7 CPE router.|Manage CPE remotely via TR-069/TR-369.|Track CPE return rates for quality trends.

Design for Manufacturability (DFM)

Engineering practices that make a design easier, cheaper, and more reliable to manufacture at scale.

DFM checks caught via-in-pad issues.|Apply the CM’s DFM rules before tooling.|DFM review is gated in our NPI process.

Design for Test (DFT)

Techniques (scan chains, BIST, boundary scan) that improve test coverage and reduce test time and cost.

Insert scan to raise DFT coverage to 98%.|Add boundary scan for board-level DFT.|The BIST engine speeds ATE time.

Die Shrink

Migrating a chip design to a smaller process node to cut area, improve performance, or lower power and cost.

Shrink from 16 nm to 7 nm next year.|Die shrink reduces cost per wafer—if yield holds.|Leakage increased after the shrink; adjust Vt.

Digital Twin

A virtual model of a product or process synchronized with real-world data for simulation, monitoring, and optimization.

Build a digital twin of the SMT line.|Simulate thermal behavior in the twin.|Use IoT telemetry to update the twin in real time.

Edge Computing

Processing data close to where it’s generated to reduce latency, bandwidth, and privacy risks.

Run ML inference at the edge, train in cloud.|The edge gateway pre-processes video feeds.|Decide edge vs cloud split for cost and latency.

Electronic Design Automation (EDA)

Software tools for designing, verifying, and implementing chips and circuit boards.

P&R is the longest step in our EDA flow.|Renew EDA licenses for Cadence and Synopsys.|Fix DRC/LVS violations before tape-out.

End of Life (EOL)

The official phase-out of a product or component, including last-buy and last-ship milestones.

Issue an EOL notice for the legacy gateway.|Supplier EOL forces a redesign.|Plan spares to support EOL commitments.

Enterprise Resource Planning (ERP)

Integrated systems that manage finance, supply chain, manufacturing, and order fulfillment data.

Sync BOM revisions from PLM to ERP.|The MRP run in ERP drives purchase orders.|ERP tracks work orders and inventory levels.

Environmental, Social, and Governance (ESG)

A framework and set of metrics for a company’s sustainability, social impact, and governance practices.

Report Scope 1–3 emissions in the ESG report.|Design for recyclability to improve ESG scores.|Audit suppliers for ESG compliance.

Fabrication Plant (Fab)

A facility where semiconductor wafers are processed into integrated circuits.

Reserve wafer starts at the TSMC fab.|The fab’s EUV capacity is constrained.|Complete process qualification at the fab.

Field-Programmable Gate Array (FPGA)

A reconfigurable hardware device programmed to implement digital logic, used for prototyping and acceleration.

Prototype the ASIC on an FPGA board.|Encrypt the FPGA bitstream for security.|Low-latency trading uses FPGA acceleration.

Firmware

Low-level software embedded in devices that interfaces closely with hardware.

Push an OTA firmware update to fix BLE.|The bootloader firmware failed secure boot.|Update the BSP for the new SoC.

Foundry

A company that manufactures chips designed by others, providing process technology, PDKs, and fabrication services.

Choose a foundry partner for 3 nm.|The foundry updated its PDK rules.|A dual-foundry strategy reduces risk.

General Availability (GA)

The milestone when a product is fully supported and broadly available to customers.

Our GA date is set for Q3.|The release candidate precedes GA by two weeks.|Some beta features won’t make GA.

Graphics Processing Unit (GPU)

A massively parallel processor optimized for graphics and general-purpose compute tasks like AI training.

Train the model on 8x GPUs.|PCIe bandwidth limits GPU performance.|Choose between integrated and discrete GPUs.

High Bandwidth Memory (HBM)

3D-stacked DRAM placed close to the processor for very high bandwidth and energy efficiency.

Our AI accelerator uses HBM3.|HBM yield impacts overall package cost.|Compare HBM vs GDDR for the new board.

Intellectual Property Core (IP Core)

Reusable, licensable logic blocks (e.g., CPU, PCIe, DDR) integrated into SoC designs.

License a PCIe Gen5 IP core.|Integrate the CPU IP core into the SoC.|IP core royalties affect unit economics.

Internet of Things (IoT)

A network of connected devices that sense, act, and communicate, often managed via cloud services.

Our IoT platform handles device provisioning.|Secure the IoT stack with PKI.|Optimize IoT node power budgets.

Joint Test Action Group (JTAG)

A standard (IEEE 1149.1) for boundary-scan testing and on-chip debug interfaces.

Program the MCU via JTAG.|Use JTAG boundary scan for board test.|Lock down JTAG in production for security.

Just-In-Time (JIT)

An inventory strategy that aligns inbound materials with production schedules to minimize holding costs.

JIT deliveries cut warehouse inventory.|JIT is risky during supply shocks.|Accurate demand signals are key for JIT.

Kanban

A visual workflow system from Lean manufacturing that limits work-in-progress and optimizes flow.

Use a Kanban board for NPI tasks.|Set WIP limits to prevent overload.|Kanban cards control SMT replenishment.

Key Performance Indicator (KPI)

A quantifiable metric that tracks progress toward business or operational goals.

Yield is a core KPI for the fab.|On-time delivery is a top supply-chain KPI.|Track field failure rate as a quality KPI.

Lead Time

The elapsed time from placing an order to receiving it, including procurement and production steps.

MCU lead time is 52 weeks.|Dual-source to reduce lead time risk.|Lead time variability impacts safety stock.

Lithography

The process of transferring patterns onto wafers using light (DUV/EUV) during semiconductor manufacturing.

3 nm requires EUV lithography.|Consider a litho-etch-litho flow.|Reticle size limits die area.

Manufacturing Execution System (MES)

Software that manages shop-floor operations, tracking WIP, enforcing process flows, and collecting data.

Track WIP and yields in MES.|MES enforces the routing and traveler.|Integrate MES with ERP and test stations.

Mean Time Between Failures (MTBF)

A reliability metric estimating the average time between inherent failures for repairable systems.

The router’s MTBF is 1 million hours.|Calculate MTBF from field returns.|Burn-in improved the MTBF significantly.

Microarchitecture

The internal organization of a processor’s pipeline, caches, and execution units implementing an ISA.

An out-of-order microarchitecture boosts IPC.|Tuning the cache hierarchy improved perf/W.|The new microarchitecture reduces branch mispredicts.

Moore’s Law

An observation that transistor counts per chip roughly double periodically, historically driving cost/performance scaling.

Moore’s Law is slowing at advanced nodes.|Our roadmap assumes post-Moore innovations.|Optimize architecture as Moore’s Law plateaus.

New Product Introduction (NPI)

The cross-functional process that takes a product from concept through validation to volume production.

Pass the NPI gate review before pilot build.|The CM reserved an NPI line for EVT.|Our NPI checklist covers DFM/DFT and compliance.

Non-Disclosure Agreement (NDA)

A legal contract to protect confidential information shared between parties.

Sign the NDA before sharing the PDK.|Our distributor executed a channel NDA.|A mutual NDA covers the joint development.

Original Design Manufacturer (ODM)

A company that designs and manufactures products that another company brands and sells.

Use an ODM reference design for speed.|Negotiate ODM margins and MOQs.|The ODM will handle regulatory certifications.

Original Equipment Manufacturer (OEM)

A company whose brand is on the final product; often integrates components or designs from suppliers/ODMs.

We sell modules to major OEMs.|The OEM dictates the industrial design.|Land design wins in the top-5 OEMs.

PCI Express (PCIe)

A high-speed serial interface standard for connecting peripherals to CPUs/SoCs.

Validate a PCIe Gen5 x16 link.|Add PCIe retimers for signal integrity.|Configure the root complex and endpoints.

Printed Circuit Board (PCB)

A board that mechanically supports and electrically connects components via copper traces, planes, and vias.

Design a 6-layer PCB with impedance control.|PCB panelization reduces SMT cost.|Move to HDI PCB for finer pitch.

Product Lifecycle Management (PLM)

Processes and systems that manage product data and changes from concept through end-of-life.

Route ECNs through PLM for approvals.|PLM is the system of record for BOMs.|Integrate PLM with CAD and ERP for traceability.